1. Field of the Invention
The present invention concerns a signal processing circuit suitable to use for a camcorder.
2. Description of Related Art
In recent years, a camcorder capable of recording image signals picked-up by a image pick-up device or external input signals supplied from an external input terminal by a video tape recorder (VTR) or playing back video signals recorded by VTR has been popularized.
FIG. 4 shows an example of a block diagram for an existent signal processing circuit applied to the camcorder described above. A signal processing circuit shown in FIG. 4 comprises, as main blocks, a CCD 11 (Charge Coupled Device) solid state image pick-up device (hereinafter referred to simply as xe2x80x9cCCDxe2x80x9d), an auto gain control circuit 13 (hereinafter referred to as xe2x80x9cAGC circuitxe2x80x9d), an A/D converter 14, an on-screen display (OSD) 15, a camera signal processing block 20, a timing generation block 30, a burst lock block 40, a line input comb filter block 50, an external inputting phase locked loop (hereinafter referred to as xe2x80x9cPLLxe2x80x9d) circuit block 60 and the like.
The CCD 11 is adapted to optoelectronically convert an image coupled by way of a not-illustrated optical lens to an image pick-up device and output the same as image signal.
The AGC circuit 13 is adapted to conduct gain control for the image signal supplied from the CCD 11 to a switch 12 upon camera photographing or a VTR reproduced video signal supplied by way of the switch 12 upon VTR playing back.
The A/D converter 14 is adapted to convert analog image/video signals gain controlled in the AGC circuit 13. into digital image/video signals.
The on-screen display 15 serves as display control section for display of character information or the like on a monitor such as a view finder.
The camera video signal processing block 20 is constituted, for example, with an LSI (Large Scale Integration) in which a signal processing circuit 21, D/A converters 22a, 22b are disposed as a signal processing circuit system, and frequency dividers 24-27, a phase comparator 28 and a switch 29 are disposed as a clock processing circuit system.
The signal processing circuit 21 comprises various kinds of circuits for applying predetermined processing when the image signal is supplied from the CCD 11 and a YC separation comb filter for removing cross talks and noises when the reproduced video signal is supplied from the VTR (hereinafter referred to as xe2x80x9creproduced type filterxe2x80x9d).
The D/A converter 22a converts a digital luminance signal (Y signal) outputted from the signal processing circuit 21 into a analog luminance signal, while the A/D converter a 22b converts digital color (chroma) signal (C signal) outputted from the signal processing circuit 21 into an analog chromatic signal.
The timing generation block 30 controls driving timing of the CCD 11 in which a CCD driving timing generation circuit 31 and a frequency divider 32 are provided. The timing generation block 30 is also constituted with an LSI.
The burst block 40 forms a signal in synchronization with a burst signal contained in a line input signal inputted from a line input terminal T41, in which are provided a switch 41 a sync separation circuit 42, a color aburst separation circuit 43, a phase comparator 44 and a frequency divider 45. The burst lock block 40 is also constituted with an LSI.
The line input comb filter block 50 conducts YC separation processing for a line input signal inputted from the line input terminal T41, in which a YC separation comb filter (hereinafter referred to as xe2x80x9cline comb filterxe2x80x9d) 51 for conducting YC separation of the line input signal. The line input comb filter block 50 is also constituted with an LSI or the like.
The external input PLL circuit block 60 forms and supplies a clock CK, a horizontal sync signal HD and a vertical sync signal VD in synchronization with the external input signal to the on-screen display 15 when the external input signal such as the line input signal or the VTR reproduced video signal, in which a horizontal/vertical sync separation circuit 61, a phase comparator 62, a frequency divider 63, a voltage controlled oscillator (VCO) 64 and a low pass filter (LPF) 65 are provided.
The operation of the signal processing circuit 100 described above will be explained.
At first, explanation is to be made for the operation during camera recording for recording the image signal picked-up by the CCD 11 in the VTR.
Upon camera recording, the switch 12 and the switch 29 of the camera signal processing block 20 are controlled so as to be in contact with contacts t1 as shown in FIG. 4. In this case, the image signal picked-up by the CCD 11 is supplied by way of the switch 12, the AGC circuit 13, and the A/D converter 14 to the signal processing circuit 21 of the camera signal processing block 20 and applied with a predetermined processing by the signal processing circuit 21. Then, they are put to D/A conversion by the D/A converters 22a, 22b and outputted as a luminance signal Y1 and a chromatic signal C1 from terminals T22, T23 respectively and are supplied, for example, to a display circuit block or a VTR signal processing block in the succeeding stage not illustrated.
As the clock forming processing during camera recording, a clock 4Fsc four times as high as a sub-carrier signal Fsc (14.3 MHz where the television system is NTSC system, or at 17.3 MHz when the television system is PAL system), and the clock 4Fsc is used as a standard clock for operating the camcorder.
The standard clock 4Fsc is supplied to the frequency divider 24 and the frequency divider 25.
The frequency divider 24 divides the standard clock 4Fsc into 1/4, which is supplied from a terminal T25 as a sub-carrier signal Fsc. The sub-carrier signal Fsc is supplied to a not-illustrated VTR signal processing block as a modifying signal upon recording the image picked-up by the CCD 11 in VTR.
The frequency divider 25 divides the standard clock 4Fsc by a predetermined dividing ratio (for example 1/910 in a case of NTSC system and 1/1135 in a case of PAL system) and outputs the same, for example, as a horizontal sync signal to one terminal (+) of a phase comparator 28.
An output from the frequency divider 26 is supplied to the other terminal (xe2x88x92) of the phase comparator 28, and the phase comparator 28 outputs a result of phase comparison between the output from the frequency divider 25 and the output from the frequency divider 26.
The output from the phase comparator 28 is inputted by way of a terminal T24 to the low pass filter (LPF) 16 and supplied by way of the LPF 16 to the voltage control oscillator (VCO) 17. Therefore, the VCO 17 is controlled for the oscillation frequency by the output of the phase comparator 28. The output from the VCO 17 is supplied by. way of a terminal T31 to the frequency divider 32 of the timing generation block 30. The frequency divider 32 divides the output from the VCO 17 into 1/2, and the divided output is supplied as a master clock MCK from a terminal T32 by way of a terminal T28 of the camera signal processing block 20 to the frequency divider 26. The frequency divider 26 divides the master clock MCK by a divisional ratio 1/FH and outputs the same to the other terminal (xe2x88x92) of the phase comparator 28. The dividing ratio 1/FH of the frequency divider 26 is determined by the number of pixels of the CCD 11.
They constitute a PLL circuit for controlling the oscillation frequency of the VCO 17, and in a state in which the PLL circuit is locked, the master clock MCK is synchronized with the standard clock 4Fsc outputted from the crystal oscillator 23.
The master clock MCK is supplied to the CCD driving timing generation circuit 31 of the timing generation block 30, the on-screen display 15 and by way of the switch 29 of the camera signal processing block 20 to the signal processing circuit 21 and the D/A converters 22a, 22b and, further, supplied from the terminal T29 to the A/D converter 14 as a clock ADCK, so that the operation timing in each of the circuit portions is controlled in synchronization with the master clock MCK.
The output of the frequency divider 26 in the camera signal processing block 20 is supplied from the terminal T26 as the horizontal sync signal AHD to the on-screen display 15 and by way of a terminal T34 of the timing generation block 30 to the CCD driving timing generation circuit 31. Further, the output from the frequency divider 26 is supplied to the frequency divider 27 and further divided by the frequency divider 27 by a predetermined divisional ratio (for example, 1/262.5 in a case of NTSC system and 1/312.5 in a case of PAL system) and supplied from the terminal T27 as the vertical sync signal AVD to the on-screen display 15 and by way of the terminal T33 to the CCD driving timing generation circuit 31 of the timing generation block 30.
Therefore, the master clock MCK, the horizontal sync signal AHD and the vertical sync signal AVD in synchronization with the standard clock 4Fsc are supplied to the on-screen display 15 to enable display control upon camera recording.
As described above, during camera recording, the master clock MCK is locked in a state synchronized with the standard clock 4Fsc outputted from the crystal oscillator 23 by the PLL circuit constituted with the phase comparator 28 of the camera signal processing block 20 and the VCO 17, and the operation of the camera signal processing block 20, the timing generation block 30 and the on-screen display 15 is controlled by the master clock MCK.
Then, the explanation is to be made for the operation during VTR reproduction for displaying the VTR reproduced image signal reproduced by the VTR on a monitor device.
During VTR reproduction, the switch 12 and the switch 29 of the camera signal processing block 20 are controlled so as to be in contact with the contacts t2 respectively, and the switch 41 of the burst lock block 40 is controlled so as to be in contact with the contact t1.
In this case, the VTR reproduced image signal (composite signal) inputted from a terminal T42 of the burst lock block 40 is supplied by way of the switch 41 of the burst lock block 40, the AGC circuit 13 and the A/D converter 14 to the signal processing circuit 21 of the camera signal processing block 20, in which cross talks and noises in the VTR reproduced image signal are eliminated by the reproduction comb filter disposed in the signal processing circuit 21, and the video signal is separated into a luminance signal and a chroma signal. Then, they are put to D/A conversion by the D/A converters 22a, 22b, outputted from the terminals T22, T23 as the luminance signal Y1 and the chroma signal C1 respectively and then supplied to the display circuit block in the succeeding stage not illustrated.
As the clock generation processing during VTR reproduction, the standard clock 4Fsc is supplied to the terminal T21 of the camera signal processing block 20, and the standard clock 4Fsc is supplied by way of the switch 29 to the signal processing circuit 21 and the D/A converters 22a, 22b and, further, supplied as a clock ADCK by way of the terminal 29 to the A/D converter 14.
Further, the standard clock 4Fsc is supplied to the frequency divider 24, divided into 1/4 and then outputted as the sub-carrier signal Fsc from the terminal T25. The sub-carrier signal Fsc is supplied as a decoding signal for the chroma signal of the VTR to a not-illustrated VTR signal processing block.
The VTR reproduced image signal supplied to the burst lock block 40 is supplied by way of the switch 41 to the sync separation circuit 42, and the sync signal SYNC is separated in the sync separation circuit 42 and supplied by way of a terminal T46 to the horizontal/vertical sync separation circuit 61 of the external input PLL circuit block 60.
In the horizontal/vertical separation circuit 61, the sync signal SYNC is separated into a vertical sync signal V and a horizontal sync signal H, and the separated vertical sync signal VD and the horizontal sync signal HD are supplied to the on-screen display 15.
Further, the horizontal sync signal HD outputted from the horizontal/vertical separation circuit 61 is supplied to one of terminals of the phase comparator 62. Further, the output from the frequency divider 63 is supplied to the other terminal of the phase comparator 62.
The output from the phase comparator 62 is supplied by way of the LPF 65 to the VCO 64, and the output from the VCO 64 is supplied, as a clock CK, to the on-screen display 15 and also to the frequency divider 63. The clock is divided by the frequency divider 63 into 1/k and outputted to the phase comparator 62. This constitutes a PLL circuit for controlling the oscillation frequency of the VCO 64 and, in a locked state of the PLL circuit, the clock CK outputted from the VCO 64 is synchronized with the VTR reproduced image signal.
Thus, the on-screen display 15 is supplied with the clock CK, the horizontal sync signal HD and the vertical sync signal VD synchronized with the inputted VTR reproduced image signal, to thereby enable display control also during VTR reproduction.
As described above, during VTR reproduction, the camera signal processing block 20 is controlled by the standard clock 4Fsc from the crystal oscillator 23 and the external input PLL circuit block 60 generates the clock CK, the horizontal sync signal HD and the vertical sync signal VD synchronized with the VTR reproduced image signal, to . thereby enable display control by the on-screen display 15 also during VTR reproduction.
Then, explanation is to be made for the operation during line recording of recording the line input signal into the VTR.
Upon during line input, the switch 41 of the burst lock block 40 is controlled so as to be in contact with the contact t2.
In this case, the line input signal inputted from the terminal T41 of the burst lock block 40 is supplied to the line input comb filter block 50, separated by the line comb filter 51 into the luminance signal Y2 and the chroma signal C2, and supplied, for example, to a display circuit block and a VTR signal processing block in the succeeding stage not illustrated.
As the clock generation processing during line input, the line input signal supplied to the burst lock block 40 is supplied by way of the switch 41 to the sync separation circuit 42 and the color burst separation circuit 43.
In the sync separation circuit 42, the sync signal SYNC contained in the line input signal is separated and supplied to the horizontal/vertical sync separation circuit 61 of the external input PLL circuit block 60, and the same processing as described for the VTR reproduction is conducted, and the clock CT, the horizontal sync signal HD and the vertical sync signal VD are supplied in synchronization with the line input signal to the on-screen display 15. Thus, display control can be conducted in the on-screen display 15 also during line input.
On the other hand, in the color burst separation circuit 43 of the burst lock block 40, the color burst signal contained in the line input signal is separated and outputted to one terminal (xe2x88x92) of the phase comparator 44. Further, the output from the frequency divider 45 is supplied to the other terminal (+) of the phase comparator 44.
The output from the phase comparator 44 is inputted by way of a terminal T44 to the LPF 46 and then supplied through the LPF 46 to the VCO 47. The output from the VCO 47 is supplied to the frequency divider 45 divided by 1/4 and outputted to the phase comparator 44. Thus, the PLL circuit for controlling the oscillation frequency of the VCO 47 is constituted. In the locked state of the PLL circuit, the oscillation frequency 4Fscxe2x80x2 from the VCO 47 is synchronized with the sub-carrier Fscxe2x80x2 of the line input signal. The VCO 47 is constituted as a crystal VCO formed by the provision of a quartz oscillator.
Then, the oscillation frequency 4Fscxe2x80x2 of the VCO 47 is supplied to the line input comb filter block 50. The oscillation frequency of the VCO 47 (standard clock) 4Fscxe2x80x2 is supplied as a decoding signal upon recording the chroma signal in the line input signal in the VTR to a not-illustrated VTR signal processing block.
As described above, during line input, the sub-carrier 4Fscxe2x80x2 four times as high as the line input signal is formed by the PLL circuit constituted with the VCO 47 and the phase comparator 44 of the burst lock block 40, so that the operation timing of the line input form filter block 50 is controlled, as well as the clock CK, the horizontal sync signal HD and the vertical sync signal VD synchronized with the line input signal are generated by the external input PLL circuit block 60, to thereby enable display control by the on-screen display 15 also during line input.
By the way, the signal processing circuit 100 provided in the camcorder of the prior art requires the external input PLL circuit block 60 for generating the line input signal and the clock CK, the horizontal sync signal HD and the vertical sync signal VD synchronized with the VTR reproduced image signal to the on-screen display 15 in order to display character information and the like on the monitor such as a view finder also during line input or VTR reproduction, to complicate the circuit structure.
Further, since the sub-carrier frequency is different between the camera recording and VTR reproduction, and the line input, it is necessary to provide a standard clock for generating the sub-carrier Fsc during camera recording and VTR reproduction (crystal oscillator 23) and a standard clock for generating the sub-carrier Fscxe2x80x2 during line input (VCO 47), respectively.
Furthermore, since the standard clock is different between the camera recording and the VTR reproduction, and the line input as described above, a line comb filter corresponding to the line input signal can not be constituted by utilizing the signal processing circuit 21 of the camera signal processing block 20, to which the standard clock in synchronization with the VTR reproduced video signal is supplied and it is necessary to additionally constitute the line input comb filter block 50.
In view of the above, the present invention has been accomplished in order to solve such problems and it is an object of the invention to simplify the structure of a signal processing circuit applied to a camcorder.
The foregoing object can be attained by a signal processing circuit provided in a camcorder having an image pick-up means for outputting a picked-up image as a picked-up video signal and a video tape recorder capable of recording/reproducing the video signal, and a line input means for inputting a video signal supplied from an outside, comprising:
a signal processing means which can conduct signal processing of separating the inputted video signal into at least a luminance signal component and a chroma signal component,
on-screen display means capable of superimposing a required image signal on a video signal outputted from the signal processing means,
a standard frequency oscillation means capable of generating a standard oscillation frequency based on a sub-carrier frequency Fsc by inputting a voltage of a predetermined fixed value to a quartz oscillation type voltage controlled oscillation means formed by the provision of a quartz oscillator,
a horizontal sync signal extraction means capable of selectively inputting one of a reproduced video signal reproduced by the video tape recorder and a line input video signal inputted by the line input means and extracting and outputting a horizontal sync signal from the inputted video signal,
a first phase locked loop circuit operating by the input of one of the frequency signal based on the standard oscillation frequency and the horizontal sync signal extracted by the horizontal sync signal extraction means as the input signal,
a second phase locked loop circuit operating by the input of the sub-carrier frequency extracted from the line input signal as the input signal and by utilizing the quartz oscillation type voltage controlled oscillation means, and
an operation control means which conducts operation of:
supplying a frequency signal obtained based on the output of a first clock generation means operating by the input of the frequency signal based on the standard oscillation frequency, as an operation clock, to the signal processing means, the on-screen display means and an optoelectronic conversion means forming the image pick-up means, when the image picked-up video signal is inputted to the signal processing means,
supplying a frequency signal based on the standard oscillation frequency, as an operation clock, to the signal processing means and supplying a frequency signal obtained based on the output of the first clock generation means operating by the input of the horizontal sync signal of the reproduced video signal extracted by the horizontal sync signal extraction means, as an operation clock, to the on-screen display means, when the reproduced video signal is inputted to the signal processing means and
supplying a frequency signal obtained based on the output of the second phase locked loop circuit, as an operation clock, to the signal processing means and supplying the frequency signal obtained based on the output of the first clock generation means operating by the input of the horizontal sync signals of the line input video signal extracted by the horizontal sync signal extraction means, as an operation clock, to the on-screen display means when the line input video signal is inputted to the signal processing means.
Further, according to the present invention, the signal processing circuit provided in a camcorder having an image pick-up means for outputting a picked-up image as a picked-up video signal and a video tape recorder capable of recording/reproducing the video signal, comprises:
a signal processing means which can conduct signal processing of separating the inputted video signal into at least a luminance signal component and a chroma signal component,
an on-screen display means capable of superimposing a required image signal on a video signal outputted from the signal processing means,
a standard frequency oscillation means capable of generating a standard oscillation frequency based on a sub-carrier frequency Fsc,
a horizontal sync signal extraction means capable of extracting and outputting a horizontal sync signal from the reproduced video signal reproduced by the video tape recorder,
a first phase locked loop circuit operating by the input of one of the frequency signal based on the standard oscillation frequency and the horizontal sync signal extracted by the horizontal sync signal extraction means as the input signal, and
an operation control means which conducts operation of:
supplying a frequency signal obtained based on the output of a first clock generation means operating by the input of the frequency signal based on the standard oscillation frequency, as an operation clock, to the signal processing means, the on-screen display means and an optoelectronic conversion means forming the image pick-up means, when the image picked-up video signal is inputted to the signal processing means,
supplying a frequency signal based on the standard oscillation frequency, as an operation clock, to the signal processing means and supplying a frequency signal obtained based on the output of the first clock generation means operating by the input of the horizontal sync signal of the reproduced video signal extracted by the horizontal sync signal extraction means, as an operation clock, to the on-screen display means, when the reproduced video signal is inputted to the signal processing means.
According to the present invention, since the frequency signal obtained based on the output from the first clock generation means operating by input of the frequency signal based on the standard oscillation frequency is supplied to the on-screen display means when the pick-up video signal is inputted to the signal processing means, the frequency signal obtained based on the output of the first clock generation means operating by input of the horizontal sync signal of the reproduced video signal extracted from the horizontal sync signal extraction means is supplied to the on-screen display means when the reproduced video signal is inputted, and the frequency signal obtained based on the output from the first clock generation means operating by input of the horizontal sync signal of the line input video signal extracted by the horizontal sync signal extraction means is supplied to the on-screen display means when the input image signal is inputted, the on-screen display means can be controlled also in a case of inputting the picked-up video signal, the reproduced video signal and the line input video signal.
Further, since the frequency signal based on the standard oscillation frequency is supplied, as the operation clock, to the signal processing means when the reproduced video signal is inputted to the signal processing means, and the frequency signal obtained based on the output from the second phase locked loop circuit is supplied, as the operation clock, to the signal processing means when the line input video signal is inputted, the reproduced video signal and the line input video signal can be separated into the luminance signal component and the chroma signal component by the signal processing means.